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 Products > Analog - Interface > LVDS Circuits > Bus LVDS Tranceivers and Repeaters > DS92LV010A

DS92LV010A  Product Folder

Bus LVDS 3.3/5.0V Single Transceiver
Generic P/N 92LV010A
General
Description
Features Datasheet Package
& Models
Samples
& Pricing
Reliability
Metrics
Application
Notes

Parametric Table Parametric Table
Temperature Min (deg C) -40 
Temperature Max (deg C) 85 
Supply Voltage (Volt)
OtherSupply Voltage 3.3V or 5V 
Function Tranceiver 
Data Rate (Mbps) 155 
Drivers ()
Receivers ()

Datasheet

TitleSize in KbytesDate
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Download

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DS92LV010A Bus LVDS 3.3 5.0V Single Transceiver 141 Kbytes 9-Oct-98 View Online Download Receive via Email
DS92LV010A Bus LVDS 3.3 5.0V Single Transceiver (JAPANESE)
312 Kbytes   View Online Download Receive via Email

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Package Availability, Models, Samples & Pricing

Part NumberPackageStatusModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
TypePinsMSL/Lead-Free AvailabilityLead
Time
QtySPICEIBISQty$US each
DS92LV010ATMSOIC NARROW8StatusFull productionN/Ads92lv010atm.ibs24 Hour Samples
Buy Now
1K+$1.50rail
of
95
NSXYTT
LV010
ATM
6-8 weeks3000
DS92LV010ATMXSOIC NARROW8StatusFull productionN/AN/A 1K+$1.50reel
of
2500
NSXYTT
LV010
ATM
6-8 weeks25000

General Description

The DS92LV010A is one in a series of transceivers designed specifically for the high speed, low power proprietary bus backplane interfaces. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. To minimize bus loading the driver outputs and receiver inputs are internally connected. The logic interface provides maximum flexibility as 4 separate lines are provided (DIN, DE, RE#, and ROUT). The device also features flow through which allows easy PCB routing for short stubs between the bus pins and the connector. The driver has 10 mA drive capability, allowing it to drive heavily loaded backplanes, with impedance as low as 27 Ohms.

The driver translates between TTL levels (single-ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition the differential signaling provides common mode noise rejection of ±1V.

The receiver threshold is ±100mV over a ±1V common mode range and translates the low voltage differential levels to standard (CMOS/TTL) levels.

Features

  • Bus LVDS Signaling (BLVDS)
  • Designed for Double Termination Applications
  • Balanced Output Impedance
  • Lite Bus Loading 5pF typical
  • Glitch free power up/down (Driver disabled)
  • 3.3V or 5.0V Operation
  • ±1V Common Mode Range
  • ±100mV Receiver Sensitivity
  • High Signaling Rate Capability (above 100 Mbps)
  • Low Power CMOS design
  • Product offered in 8 lead SOIC package
  • Industrial Temperature Range Operation

Reliability Metrics

Part Number Process Early Failure Rate - Rejects Sample Size (EFR) PPM * Rel. Rejects Device Hours Long Term Failure Rates (FITS) MTTF
DS92LV010ATMCS0801322200586013460009011224278
DS92LV010ATMXCS0801322200586013460009011224278

For more information on Reliablitity Metrics, please click here.


Application Notes

TitleSize in KbytesDate
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AN-1115: Application Note 1115 DS92LV010A Bus LVDS Transceiver Ushers in a New Era of High-Performance Backplane Design 110 Kbytes 24-Aug-98 View Online Download Receive via Email
AN-1088: Application Note 1088 LVDS Signal Quality: Cable Drive Measurements using Eye Patterns Test Report #3 130 Kbytes 2-Mar-99 View Online Download Receive via Email

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 15-Jan-2004]