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FPD85310  Product Folder

Panel Timing Controller [Preliminary]
Generic P/N 85310
General
Description
Features Datasheet Package
& Models
Samples
& Pricing
Reliability
Metrics

Datasheet

TitleSize in KbytesDate
View Online

Download

Receive via Email
FPD85310 Panel Timing Controller 440 Kbytes 7-Sep-99 View Online Download Receive via Email

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Package Availability, Models, Samples & Pricing

Part NumberPackageStatusModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
TypePinsMSL/Lead-Free AvailabilityLead
Time
QtySPICEIBISQty$US each
FPD85310XXX/VJDTQFP100StatusPreliminaryN/AN/A   tray
of
N/A
NSUZXYYTTES
FPD85310-XXX
/VJDBBBBB
N/A

Obsolete Parts

Obsolete PartAlternate Part or SupplierSourceLast Time Buy Date
FPD85310CLA/VJD

NONE
06/03/2003
FPD85310CPA/VJD

NONE
06/03/2003
FPD85310CSA/VJD

NONE
12/04/2001
FPD85310CSA/VJD

NONE
06/03/2003
FPD85310CSC/VJD

NONE
03/05/2002
FPD85310CSF/VJD

NONE
06/03/2003
FPD85310VJD

NONE
06/03/2003

General Description

The FPD85310 Panel Timing Controller is an integrated FPD-Link based TFT-LCD timing controller. It resides on the flat panel display and provides the interface signal routing and timing control between graphics or video controllers and a TFT-LCD system. FPD-Link is a low power, low electromagnetic interference interface used between this controller and the host system.

The FPD85310 chip links the panel's system interface to the display via a ten wire LVDS data bus. That data is then routed to the source and gate display drivers. XGA and SVGA resolutions are supported.

The FPD85310 is programmable via an optional external serial EEPROM. Reserved space in the EEPROM is available for display identification information. The system can access the EEPROM to read the display identification data or program initialization values used by the FPD85310.

Features

  • FPD-Link System Interface utilizes Low Voltage Differential Signaling (LVDS).
  • System programmable via EEPROM
  • Suitable for notebook and monitor applications
  • 8-bit or 6-bit system interface
  • XGA or SVGA capable
  • Supports single or dual port column drivers
  • Programmable outputs provide customized control for standard or in-house column drivers and row drivers
  • Fail-safe operation prevents panel damage with system clock failure
  • Programmable skew rate controlled outputs on CD interface for reduced EMI
  • Polarity pin reduces CD data bus switching
  • CMOS circuitry operates from a 3.3V supply

Reliability Metrics

Part Number Process Early Failure Rate - Rejects Sample Size (EFR) PPM * Rel. Rejects Device Hours Long Term Failure Rates (FITS) MTTF
FPD85310XXX/VJDCMOS721420014108000005226190940

For more information on Reliablitity Metrics, please click here.


[Information as of 15-Jan-2004]