PC87360  Product Folder

The PC87360 is the first member of National SemiconductorÆs 128-pin SuperI/O family to support the Low Pin Count (LPC) interface. It provides features to protect the system design and supports 45 GPIO ports, many with Assert IRQ/#SMI/#PWUREQ capability. The PC87360 is PC99 and ACPI compliant and offers a single-chip solution to the most commonly used PC I/O peripherals.

The PC87360 also incorporates: Fan Speed Control and Monitoring for two fans, a Floppy Disk Controller (FDC), a Keyboard and Mouse Controller (KBC), an ACCESS.bus® Interface (ACB), System Wake-Up Control (SWC), Interrupt Serializer for Parallel IRQs, an enhanced WATCHDOG Timer, a full IEEE 1284 Parallel Port and two enhanced Serial Ports (UARTs), one with Infrared (IR) support.

Outstanding Features

• Bus interface, based on IntelÆs LPC Interface Specification Revision 1.0, September 29th, 1997
• Protection features, including I/O access lock, GPIO lock and pin configuration lock
• 45 GPIO Ports (37 standard, including 23 with Assert IRQ/#SMI/#PWUREQs interrupts; 8 V_SB powered)
• Fan Speed Control and Monitor for two fans
• Interrupt Serializer (11 Parallel IRQs to Serial IRQ)
• Serial IRQ support (15 options)
• ACCESS.bus Interface, compatible with SMbus® physical layer
• Blinking LEDs
• 128-pin PQFP Package

• LPC System Interface
• Synchronous cycles, up to 33 MHz bus clock
• 8-bit I/O cycles
• Up to four DMA channels
• 8-bit DMA cycles
• Basic read, write and DMA bus cycles are 13 clock cycles long

• Protection
• Access lock to I/O ports (#XLOCK)
• GPIO lock
• Pin configuration lock

• 45 General-Purpose I/O (GPIO) Ports
• 37 standard, with Assert IRQ/#SMI/#PWUREQ for 23 ports
• Eight V_SB powered
• Programmable drive type for each output pin (open-drain, push-pull or output disable)
• Programmable option for internal pull-up resistor on each input pin
• Output lock option
• Input debounce mechanism

• PC99 and ACPI Compliant
• PnP Configuration Register structure
• Flexible resource allocation for all logical devices
• Relocatable base address
• 15 IRQ routing options
• Four optional 8-bit DMA channels (where applicable)

• Fan Speed Control and Fan Speed Monitor (FSCM)
• Supports different fan types
• Speed monitoring for two fans
• Digital filtering of the tachometer input signal
• Alarm for fan slower than programmable threshold speed
• Alarm for fan stop
• Two speed control lines with Pulse Width Modulation (PWM)
• Output signal in the range of 6 Hz to 93.75 KHz
• Duty cycle resolution of 1/256

• Interrupt Serializer
• 11 Parallel IRQs to Serial IRQ

• Floppy Disk Controller (FDC)
• Programmable write protect
• FM and MFM mode support
• Enhanced mode command for three-mode Floppy Disk Drive (FDD) support
• Perpendicular recording drive support for 2.88 MB
• Burst and non-burst modes
• Full support for IBM Tape Drive register (TDR) implementation of AT and PS/2 drive types
• 16-byte FIFO
• Software compatible with the PC8477, which contains a superset of the FDC functions in the microDP8473, the NEC microPD765A and the N82077
• High-performance, digital separator
• Standard 5.25" and 3.5" FDD support

• Parallel Port
• Software or hardware control
• Enhanced Parallel Port (EPP) compatible with new version EPP 1.9 and IEEE 1284 compliant
• EPP support for version EPP 1.7 of the Xircom spec-ification
• EPP support as mode 4 of the Extended Capabilities Port (ECP)
• IEEE 1284-compliant ECP, including level 2
• Selection of internal pull-up or pull-down resistor for Paper End (PE) pin
• PCI bus utilization reduction by supporting a demand DMA mode mechanism and a DMA fairness mechanism
• Protection circuit that prevents damage to the parallel port when a printer connected to it powers up or is operated at high voltages, even if the device is in power-down
• Output buffers that can sink and source 14 mA

• Serial Port 1 (UART1)
• Software compatible with the 16550A and the 16450
• Shadow register support for write-only bit monitoring
• UART data rates up to 1.5 Mbaud

• Serial Port 2 with Infrared (UART2)
• Software compatible with the 16550A and the 16450
• Shadow register support for write-only bit monitoring
• UART data rates up to 1.5 Mbaud
• HP-SIR
• ASK-IR option of SHARP-IR
• DASK-IR option of SHARP-IR
• Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS 80
• Non-standard DMA support - one or two channels
• PnP dongle support

• Keyboard and Mouse Controller (KBC)
• 8-bit microcontroller
• Software compatible with the 8042AH and PC87911 microcontrollers
• 2 KB custom-designed program ROM
• 256 bytes RAM for data
• Five programmable dedicated open-drain I/O lines
• Asynchronous access to two data registers and one status register during normal operation
• Support for both interrupt and polling
• 93 instructions
• 8-bit timer/counter
• Support for binary and BCD arithmetic
• Operation at 8 MHz,12 MHz or 16 MHz (programmable option)
• Can be customized by using the PC87323, which includes a RAM-based KBC as a development plat-form for KBC code

• ACCESS.bus Interface (ACB)
• Serial interface compatible with SMbus physical layer
• Compatible with PhilipsÆ I²C®
• ACB master and slave
• Supports polling and interrupt controlled operation
• Optional internal pull-up on SDA and SCL pins

• WATCHDOG Timer
• Times out the system based on user-programmable time-out period
• System power-down capability for power saving
• User-defined trigger events to restart WATCHDOG
• Optional routing of WATCHDOG output on IRQ and/or #SMI lines

• System Wake-Up Control (SWC)
• Power-up request upon detection of Keyboard, Mouse, #RI1, #RI2, #RING activity and General-Purpose Input Events, as follows:
• Preprogrammed Keyboard or Mouse sequence
• External modem ring on serial port
• Ring pulse or pulse train on the RING input signal
• Preprogrammed CEIR address in a preselected standard (NEC, RCA or RC-5)
• General-Purpose Input Events
• IRQs of internal logical devices
• Optional routing of power-up request on IRQ and/or SMI lines
• Battery-backed event configuration
• Programmable V_SB-powered output for blinking LEDs (LED1, LED2) control

• Clock Sources
• 48 MHz clock input
• LPC clock, up to 33 MHz
• On-chip low-frequency clock generator for wake-up

• Power Supplies
• 3.3V supply operation
• Main (V_DD )
• Standby (V_SB )
• Battery backup (V_BAT )
• All pins are 5V tolerant and back-drive protected, except LPC bus pins

• Strap Configuration
• Base Address (BADDR) strap to determine the base address of the Index-Data register pair
• Test strap to force the device into test mode (reserved for National Semiconductor use)

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