PC87372  Product Folder

The National Semiconductor® PC87372 Advanced I/O product is a member of the PC8737x SuperI/O family. All PC8737x devices are highly integrated and are pin and software compatible, thus providing drop-in interchangeability and enabling a variety of assembly options using only a single motherboard and BIOS.

PC87372 integration allows for a smaller system board size and saves on total system cost.

The PC87372 includes legacy SuperI/O functions, system glue functions, fan monitoring and control, commonly used functions such as GPIO, and ACPI-compliant Power Management support.

The PC87372 integrates miscellaneous analog and digital system glue functions to reduce the number of discrete components required. The host communicates with the functions integrated in the PC87372 device through an LPC Bus Interface.

The PC87372 Legacy functions are: a serial port (UART), a fully compliant IEEE 1284 Parallel Port, a Floppy Disk Controller (FDC) and a Keyboard/Mouse Controller (KBC).

The Fan Speed Monitor (FSM) module allows the system to monitor two fans.

The PC87372 extended wake-up support complements the ACPI controller in the chipset. The System Wake-Up Control (SWC) module, powered by V_SB3, supports a flexible wake-up mechanism.

There are 13 General-Purpose Input/Output (GPIO) ports; these allow system control and wake-up on system events.

Outstanding Features

• Legacy modules: Parallel Port, Floppy Disk Controller (FDC), Serial Port (UART) and a Keyboard and Mouse Controller (KBC)
• Glue functions to complement the South Bridge functionality
• Fan Speed Monitor for two fans
• V_SB3-powered Power Management with 20 wake-up sources
• Controls three LED indicators
• 13 GPIO ports with a variety of wake-up options
• LPC interface, based on IntelÆs LPC Interface Specification Revision 1.0, September 29th, 1997
• PC01 Revision 1.0 and Advanced Configuration and Power Interface (ACPI) Specification Revision 2.0 compliant
• 128-pin PQFP package

Bus Interface

• LPC Bus Interface
• Based on IntelÆs LPC Interface Specification Revision 1.0, September 29, 1997
• Synchronous cycles using up to 33 MHz bus clock
• 8-bit I/O read and write cycles
• Up to four 8-bit DMA channels
• Serial IRQ (SERIRQ)
• Reset input (#PCI_RESET)
• Optional power-down support (#LPCPD)
• Configuration Control
• PnP Configuration Register structure
• Compliant with PC01 Specification Revision 1.0, 1999-2000
• Base Address strap (#BADDR) to setup the address of the Index-Data register pair (defaults to 2Eh/2Fh)
• Flexible resource allocation for all logical devices:
• Relocatable base address
• 15 IRQ routing options to serial IRQ
• Up to four optional 8-bit DMA channels
• Configurable feature sets:
• Software selectable
• V_SB3-powered pin multiplexing

Legacy Modules

• Serial Port
• Software compatible with the NS16550A and the NS16450
• Supports shadow register for write-only bit monitoring
• Data rates up to 1.5 Mbaud
• IEEE 1284-compliant Parallel Port
• ECP, with Level 2 (14 mA sink and source output buffers)
• Software or hardware control
• Enhanced Parallel Port (EPP) compatible with EPP 1.7 and EPP 1.9
• Supports EPP as mode 4 of the Extended Control Register (ECR)
• Selection of internal pull-up or pull-down resistor for Paper End (PE) pin
• Supports a demand DMA mode mechanism and a DMA fairness mechanism for improved bus utilization
• Protection circuit that prevents damage to the parallel port when a printer connected to it is powered up or is operated at high voltages (in both cases, even if the PC87372 is in power-down state)
• Floppy Disk Controller (FDC)
• Software compatible with the PC8477 (the PC8477contains a superset of the FDC functions in the microDP8473, NEC microPD765A/B and N82077 devices)
• Error-free handling of data overrun and underrun
• Programable write protect
• Supports FM and MFM modes
• Supports Enhanced mode command for three-mode Floppy Disk Drive (FDD)
• Perpendicular recording drive support for 2.88 MByte
• Burst (16-byte FIFO) and Non-Burst modes
• Full support for IBM Tape Drive Register (TDR) implementation of AT and PS/2 drive types
• High-performance digital separator
• Supports fast tape drives (2 Mbps) and standard tape drives (1 Mbps, 500 Kbps and 250 Kbps)
• Keyboard and Mouse Controller (KBC)
• 8-bit microcontroller, software compatible with 8042AH and PC87911
• Standard interface (60h, 64h, IRQ1 and IRQ12)
• Supports two external swapable PS/2 interfaces for keyboard and mouse
• Programable, dedicated quasi-bidirectional I/O lines (GA20/P21, #KBRST/P20)

General-Purpose Modules

• General-Purpose I/O (GPIO) Ports
• 13 GPIO ports powered by V_SB3
• Each pin individually configured as input or output
• Programable features for each output pin:
• Drive type (open-drain, push-pull or TRI-STATE®)
• TRI-STATE on detection of falling V_DD3 for V_SB3-powered pins driving V_DD-supplied devices
• Programable option for internal pull-up resistor on each input pin
• Lock option for the configuration and data of each output pin
• 12 GPIO ports generate IRQ/#SIOPME for wake-up events; each GPIO has separate:
• Enable control of event status routing to IRQ
• Enable control of event status routing to #SIOPME
• Polarity and edge/level selection
• Programable debouncing
• Glue Functions
• Software selectable alternative functionality, through pin multiplexing
• Generates the power-related signals:
• Main Power good
• Power distribution control (for switching between Main and Standby regulators)
• Resume reset (Master Reset) according to the 5V standby supply status
• Main power supply turn on (#PS_ON)
• Rambus SCK clock gating
• Voltage translation between 3.3V levels (DDC) and 5V levels (VGA) for the SMBus serial clock and data signals
• Isolation circuitry for the SMBus serial clock and data signals
• Buffers #PCI_RESET to generate three reset output signals
• Generates "highest active supply" reference voltage
• Based on 3.3V and 5V Main supplies
• Based on 3.3V and 5V Standby supplies
• High-current LED driver control for Hard Disk Drive activity indication
• CNR downstream codec, dynamic control
• Fan Speed Monitor (FSM)
• Supports tachometers with one or two pulses per revolution
• Speed monitoring for two fans, including:
• Digital filtering of the tachometer input signal
• 16-bit fan speed data
• Alarm for fan speed slower than programmed threshold
• Alarm for fan stopped

Power Management

• Supports ACPI Specification Revision 2.0b, July 27, 2000
• System Wake-Up Control (SWC)
• Optional routing of events to generate SCI (#SIOPME) on detection of:
• Keyboard or Mouse events
• Ring Indication #RI on the serial port
• General-Purpose Input Events from the 12 GPIO pins
• IRQs of the Keyboard and Mouse Controller
• IRQs of the other internal modules
• Optional routing of the SCI (#SIOPME) to generate IRQ (SERIRQ)
• Implements the GPE1_BLK of the ACPI General Purpose (Generic) Register blocks with "child" events
• V_SB3-powered event detection and event-logic configuration
• Enhanced Power Management (PM), including:
• Special configuration registers for power down
• Low-leakage pins
• Low-power CMOS technology
• Ability to disable all modules
• High-current LED drivers control (two LEDs) for power status indication with:
• Standard blinking, controlled by software
• Advanced blinking, controlled by power supply status, Sleep state or software
• Keyboard Events
• Wake-up on any key
• Supports programable 8-byte sequence "Password" or "Special Keys" for Power Management
• Simultaneous recognition of three programable keys (sequences): "Power", "Sleep" and "Resume"
• Wake-up on mouse movement and/or button click

Clocking, Supply, and Package Information

• Clocks
• LPC (PCI) clock input (up to 33 MHz)
• Low-frequency 32.768 KHz clock input, active also in S3-S5 (when V_DD3is off), for:
• System Wake-Up Control (SWC) wake-up timing
• LED blink timing
• Glue Functions timing
• On-chip Clock Generator:
• Generates 48 MHz for the SuperI/O modules and FSM
• Based on the 14.31818 MHz clock input
• V_DD3-powered
• Protection
• All device pins are 5V tolerant and back-drive protected (except LPC bus pins)
• High ESD protection of all the device pins
• Pin multiplexing configuration lock
• Configuration register lock
• Testability
• XOR tree structure
• Includes all the device pins (except the supply and the analog pins)
• Selected at power-up by strap input (#TEST)
• TRI-STATE device pins, selected at power-up by strap input (#TRIS)
• Power Supply
• 3.3V supply operation
• Separate pin pairs for main (V_DD3) and standby (V_SB3) power supplies
• Separate pin for core voltage filtering (V_CORF)
• Low standby power consumption
• Package
• 128-pin PQFP

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