SCANPSC100F  Product Folder

The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor. The 'PSC100F operates by serializing data from the parallel bus for shifting through the chain of 1149.1 compliant components (i.e., scan chain). Scan data returning from the scan chain is placed on the parallel port to be read by the host processor. Up to two scan chains can be directly controlled with the 'PSC100F via two independent TMS pins. Scan control is supplied with user specific patterns which makes the 'PSC100F protocol-independent. Overflow and underflow conditions are prevented by stopping the test clock. A 32-bit counter is used to program the number of TCK cycles required to complete a scan operation within the boundary scan chain or to complete a 'PSC100F Built-In Self Test (BIST) operation. SCANPSC100F device drivers and 1149.1 embedded test application code are available with National's SCANEase software tools.

• Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
• Supported by National's SCAN Ease (Embedded Application Software Enabler) Software
• Uses generic, asynchronous processor interface; compatible with a wide range of processors and PCLK frequencies
• Directly supports up to two 1149.1 scan chains
• 16-bit Serial Signature Compaction (SSC) at the Test Data In (TDI) port
• Automatically produces pseudo-random patterns at the Test Data Out (TDO) port
• Fabricated on FACT™ 1.5 µm CMOS process
• Supports 1149.1 test clock (TCK) frequencies up to 25 MHz
• TTL-compatible inputs; full-swing CMOS outputs with 24 mA source/sink capability
• Standard Microcircuit Drawing (SMD) 5962-9475001