USBN9603  Product Folder

The USBN9603/4 are integrated, USB Node controllers.

The only difference between the USBN9603 and USBN9604 devices is the effect of a hardware reset on the clock generation circuit. In the USBN9604, assertion of the RESET input causes the clock generation circuit to be reset, the same as during Power-on reset, whereas in the USBN9603 the clock generation circuit is not reset.

This difference is particularly important for bus-powered operations. In such applications, the voltage provided by the bus may fall below acceptable levels for the clock generation circuit. When this occurs, a reset must be applied to this circuit to guarantee proper operation. This low voltage detection is typically accomplished in bus-powered applications using a voltage sensor such as the LP3470 to appropriately reset the CPU and other components including the USBN9604.

Other than the reset mechanism for the clock generation circuit, these two devices are identical. All references to "the device" in this document refer to both devices, unless otherwise noted.

The device provides enhanced DMA support with many automatic data handling features. It is compatible with USB specification versions 1.0 and 1.1, and is an advanced  version of the USBN9602.

The device integrates the required USB transceiver with a 3.3V regulator, a Serial Interface Engine (SIE), USB end-point (EP) FIFOs, a versatile 8-bit parallel interface, a clock generator and a MICROWIRE/PLUSÖ interface. Seven endpoint pipes are supported: one for the mandatory control endpoint and six to support interrupt, bulk and isochronous endpoints. Each endpoint pipe has a dedicated FIFO, 8 bytes for the control endpoint and 64 bytes for the other endpoints. The 8-bit parallel interface supports multiplexed and non-multiplexed style CPU address/data buses. A programmable interrupt output scheme allows device configuration for different interrupt signaling requirements.

• Full-speed USB node device
• Integrated USB transceiver
• Supports 24 MHz oscillator circuit with internal 48 MHz clock generation circuit
• Programmable clock generator
• Serial Interface Engine (SIE) consisting of Physical Layer Interface (PHY) and Media Access Controller (MAC), USB Specification 1.0 and 1.1 compliant
• Control/Status register file
• USB Function Controller with seven FIFO-based End-points:
• One bidirectional Control Endpoint 0 (8 bytes)
• Three Transmit Endpoints (64 bytes each)
• Three Receive Endpoints (64 bytes each)
• 8-bit parallel interface with two selectable modes:
• Non-multiplexed
• Multiplexed (Intel compatible)
• Enhanced DMA support
• Automatic DMA (ADMA) mode for fully CPU-independent transfer of large bulk or ISO packets
• DMA controller, together with the ADMA logic, can transfer a large block of data in 64-byte packets via the USB
• Automatic Data PID toggling/checking and NAK packet recovery (maximum 256x64 bytes of data =16K bytes)
• MICROWIRE/PLUS interface