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National Semiconductor's CompactRISC architecture was created from the ground up as an alternative solution to CISC and other accumulator based architectures. The CompactRISC architecture is a RISC architecture specifically designed for embedded systems. It features the best of RISC and CISC with compact code generation, low power consumption, silicon-efficient implementations, the ability to tightly integrate on-chip acceleration, I/O and memory functions.
CompactRISC implementations greatly reduce the amount of silicon required for the CPU, code memory and data memory, without significantly reducing the overall performance advantages of RISC. In addition, because any processing core is only as good as its peripheral support, several key architectural decisions were made to optimize bus structures and I/O control for embedded systems in order to improve flexibility and reduce costs.
Since its introduction, the CompactRISC architecture has firmly established itself by filling a previously unmet market gap - those embedded applications that require the performance of RISC, but cannot afford the processing and cost overhead of 32-bit RISC implementations. The 16-bit CompactRISC family of cores has been particularly popular with designers because of its optimal balance of cost and performance, plus the ability to combine a very small-size core with other key on-chip functions.
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