Objective:

To get an understanding of PLL performance. Includes phase noise, lock time and spurs.

Reading Assignment:

• PLL Performance presentation and slide notes

Additional Resources:

• PLL Performance, Simulation and Design, by Dean Banerjee             
• Single Integer PLL Parametric Selection Guide: Wireless.national.com

Research Assignment:

1. Define Lock time (Switching time). check answer
   
   
2. If I keep the same comparison frequency, but double the N counter value, what is the impact on phase noise inside the loop bandwidth? check answer
   
   
3. Which of these PLLs does not have Fastlock? check answer
   a) LMX2306
   b) LMX2310U
   c) LMX2311U
   d) LMX2324

Program Coordinator/Professor

Dean Banerjee

Dean Banerjee is a Senior Wireless Applications Engineer with National Semiconductor's Wireless Products division and is the author of "PLL Performance, Simulation, and Design". During this time, he has assisted in the development and support of various PLL synthesizer chips.

Quiz:

Take this Quiz to check your understanding of this subject.

Answer all questions correctly to receive a certificate from Dean Bob Pease.