Objective:

To gain an understanding of Fractional PLLs. Including Sigma Delta Fractional PLLs, traditional Fractional PLLs, Integer PLLs and their differences. Also discusses cycle slipping, lock time, phase noise and spur levels.

Online Seminar:

Advantages and Pitfalls of Using Fractional N PLLs (online seminar notes), February 27, 2003, by Dean Banerjee
The rise of Fractional N PLLs, and especially Sigma Delta Fractional N PLLs brings the opportunity for significant performance enhancements in some applications, but other applications favor the use of Integer N PLLs. This presentation concentrates on performance criteria of lock time, phase noise and spur levels. 

Reading Assignment:

• Fractional N PLLs presentation and slide notes

Additional Resources:

• PLL Performance, Simulation and Design, by Dean Banerjee

Research Assignment:

From the online seminar and reading material, please answer the following questions:

1. What are the three different types of fractional compensation methods? Briefly define them. check answer
   
   
2. If the comparison frequency is 19.68 MHz and the loop bandwidth of a PLL is 10 kHz, what effect would you expect for cycle slipping to have on the lock time and why? check answer
   

Program Coordinator/Professor

Dean Banerjee

Dean Banerjee is a Senior Wireless Applications Engineer with National Semiconductor's Wireless Products division and is the author of "PLL Performance, Simulation, and Design". During this time, he has assisted in the development and support of various PLL synthesizer chips.

Quiz:

Take this Quiz to check your understanding of this subject.

Answer all questions correctly to receive a certificate from Dean Bob Pease.