Objective:

To gain an understanding of Loop Filter Design and Simulation with the use WEBENCH™ EasyPLL Online Simulation Tools.

Online Seminar:

Loop Filter Optimization, April 19, 2001, by Dean Banerjee, Deborah Brown, and Khang Nguyen
This seminar discusses various issues related to passive loop filter designs and presents new techniques using EasyPLL for optimizing passive loop filters for better performance.

Reading Assignment:

1. Loop Filter Optimization presentation (and notes) from online seminar
   
   
2. WEBENCH™ EasyPLL Online Simulation Tools help
   
   
3. WIRELESS.NATIONAL.COM presentation and slide notes
   

Additional Resources:

• PLL Performance, Simulation and Design, by Dean Banerjee    

Research Assignment:

From the Loop Filter Optimization presentation (and notes) and the WEBENCH™ EasyPLL Online Simulation Tools, please answer the following questions:

1. If I have a comparison frequency of 200 KHz, approximately what is the minimum loop bandwidth I can have to change from 889 - 915 MHz to a 1 KHz tolerance in less than 500 uS? check answer
   
   
2. Suppose I have a frequency of 889-915 MHz.  What N divider value do I design for and how is it calculated? check answer
   
   
3. How do I choose my loop bandwidth to design for minimum RMS phase error? check answer
   
   
4. What does National Semiconductor's WEBENCH™ EasyPLL Online Simulation Tools have to offer a designer? check answer
   

Program Coordinator/Professor

Dean Banerjee

Dean Banerjee is a Senior Wireless Applications Engineer with National Semiconductor's Wireless Products division and is the author of "PLL Performance, Simulation, and Design". During this time, he has assisted in the development and support of various PLL synthesizer chips.

Quiz:

Take this Quiz to check your understanding of this subject.

Answer all questions correctly to receive a certificate from Dean Bob Pease.