Filtror by andy@warmcat.com  A device to share a chunk of SRAM between an LPC port and a PC Printer Port
Note   The prototype has been shown to work!

Scope 

Filtror is a small device designed to:

• Present 4Mbit of SRAM (optionally 8Mbit if a second SRAM is fitted) to an LPC-compatible connector 
• Allow the SRAM to be read and written to from a PC Printer port under Linux or Windows
• Allow the SRAM to have shared access between the PC and the LPC host at all times, such that is is possible to communicate with the host by read and writing checksum-protected arbitrary length structs to arbirary addresses inside the SRAM while the host continues to read and write unhindered

The need the device fulfils is to facilitate rapid debug and communication with an LPC-enabled host and a PC.

The design schematics, gerbers and C & VHDL sources are being released under the GPL, others are encouraged to duplicate our design when it is proven.  However, as with all GPL projects, no warrenty at all is given about the performance of this design.  It might do anything up to and including destroying the planet you are on if you build one.  However I believe it will eventually perform as suggested.

Overview

Principles

• Requires an always-on 3.3V power supply (for X-Box¹ use this is availble from  PIC pin).  This allows us to communicate with the SRAM, and maintains its contents indefinitely, even when the main host power is down.  This implies it needs a private clock oscillator, because the 33MHz LPC clock will not be available when the main host power is down.

• Not modal, that is, the host can always read and write the SRAM over LPC, and the PC can always read and write the same SRAM over the Printer Port connection without disturbance of either side.  So there is no mode where the PC has control or the host.  (this works by inserting LPC waitstates if a PC-side access is ongoing at that time).

• Appears to be a Xilinx Parallel cable while the CPLD is unconfigured or a jumper is set.  This allows the CPLD to be configured directly from the Printer Port alone without needing any Xilinx programming hardware.  (The Xilinx programming software is needed however, and is available for download from Xilinx).

• Will have the ability to drive the LPC reset pin to ensure the host is quiescent and not performing any LPC writes.  Will have a General Purpose signal that is low from powerup until the first LPC action from the host, when it becomes open-drain.  Will have the same power cycling hardware as Milksop allowing automated host restart.

• Like milksop this is a not-for-profit design.  I will not  be building and selling these boards.  However, this time I intend to build more than one and give them at no charge to the kernel hackers who need them most.   Just to be crystal clear, it costs me hundreds of pounds to create and prove these designs, which I then give away for free for other people to build.  I in no way profit from these efforts, other than collecting some kind words in email from time to time.

• This design does not do the same job as Milksop, it does not address TSOP forcing.  Because it does not contain flash it is of no use except to people who will be writing, running, and debugging code via an LPC connector.  It is of no use as a device for nonvolatile storage as it would need a PC to fill the SRAM every time you powered down the host.

Implementation

Physcial hardware

Milksop uses a Xilinx XC95144XL CPLD in a TQ100 package. 

Schematics

Click on the thumbnail to get the schematic PDF

PCB layout

Engineering Change Notice (ECN) 1

Partslist

CPLD Logic

Second draft of VHDL 2002-06-27

SVF file ready to program with milk

Host Cable

The host connector has the following pinout:

1: GND
2: (key)
3: nportNoLpcYet (for X-Box, hook to flash bus D0)
4: 3.3V 'always on' power supply input
5:  see below
6: see below

Pins 5 & 6 hook to active-low reset signal; for X-Box they need to be wired to the front panel connector pins 6 and 8 as shown below (the pin numbers refer to the connector shown, not the Host connector on Filtror)

Pin 4 of the host connector needs to be connected to an always-on 3.3V supply rail.  For the X-Box, this can be taken from p21 of the PIC, or for easier soldering, the end of the capacitor that this pin is also connected to.  0V is easily available from a nearby capacitor.

Debug connector

The Debug connector just brings out some unused IO from the CPLD to a place where I can monitor them easily.  I will be using this IO to help me see what is going on inside the CPLD if things are not working properly.  It also allows some extra signals to be added on to the design if someone has a bright idea.

CFG connector

This two-pin header is left open for normal operation.  To set Filtror into Xilinx configuration mode, where it looks like a Xilinx Parallel cable is already connected to the CPLD, link the two pins.  After configuration (or reconfiguration), remove the link for normal operation.

Progress 2002-07-03

¹X-Box is a registered trademark of Microsoft Corporation, nothing to do with us.