100341 Product Folder |
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| General Description |
Features | Datasheet | Package & Models |
Samples & Pricing |
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| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| 100341 Low Power 8-Bit Shift Register | 150 Kbytes | 17-Aug-98 | View Online | Download | Receive via Email |
| 100341 Mil-Aero Datasheet MN100341-X | 80 Kbytes | View Online | Download | Receive via Email |
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If you have trouble printing or viewing PDF file(s), see Printing Problems. |
| Part Number | Package | Status | Models | Samples & Electronic Orders | Budgetary Pricing | Std Pack Size | Package Marking | |||||
| Type | Pins | MSL/Lead-Free Availability | Lead Time | Qty | SPICE | IBIS | Qty | $US each | ||||
| 5962-9459101MXA | CERDIP | 24 | Status | Full production | N/A | N/A | 50+ | $33.80 | rail of 15 | NSZSSXXYYA> 100341DMQB /Q 5962-9459101MXA | ||
| 8-10 weeks | 500 | |||||||||||
| 5962-9459101MYA | CERQUAD | 24 | Status | Full production | N/A | N/A | | 50+ | $39.60 | rail of 14 | NSZSSXXYYA Q> FMQB 5962 -9459101 MYA | |
| 10-12 weeks | 500 | |||||||||||
| 5962-9459101VXA | CERDIP | 24 | Status | Full production | N/A | N/A | 50+ | $265.00 | rail of 15 | NSZSSXXYYA> 100341J-QMLV 5962-9459101VXA | ||
| N/A | 0 | |||||||||||
| 5962-9459101VYA | CERQUAD | 24 | Status | Full production | N/A | N/A | 50+ | $265.00 | rail of 14 | NSZSSXXYYA 100341W- QMLV 5962 -9459101 VYA > | ||
| N/A | 0 | |||||||||||
| 5962F9459101VYA | CERQUAD | 24 | Status | Full production | N/A | N/A | 50+ | $270.00 | rail of 14 | NSZSSXXYYA 100341WF QMLV 5962 F9459101 VYA > | ||
| N/A | 0 | |||||||||||
| Obsolete Part | Alternate Part or Supplier | Source | Last Time Buy Date |
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| 100341FC | NONE | NSC SYNERGY | 04/04/95 |
The 100341 contains eight edge-triggered, D-type flip-flops with individual inputs (Pn) and outputs (Qn) for parallel operation, and with serial inputs (Dn) and steering logic for bidirectional shifting. The flip-flops accept input data a setup time before the positive-going transition of the clock pulse and their outputs respond a propagation delay after this rising clock edge. The circuit operating mode is determined by the Select inputs S0 and S1, which are internally decoded to select either "parallel entry", "hold", "shift left" or "shift right" as described in the Truth Table. All inputs have 50 k Ohm pull-down resistors. |
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