54ABT377  Product Folder

The 'ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE#) is LOW.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE# input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

• Clock enable for address and data synchronization applications
• Eight edge-triggered D flip-flops
• Buffered common clock
• See 'ABT273 for master reset version
• See 'ABT373 for transparent latch version
• See 'ABT374 for TRI-STATE version
• Output sink capability of 48 mA, source capability of 24 mA
• Guaranteed latchup protection
• High impedance glitch free bus loading during entire power up and power down cycle
• Non-destructive hot insertion capability
• Disable time less than enable time to avoid bus contention
• Standard Microcircuit Drawing (SMD) 5962-9314801