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54AC273| 54AC273 Product Folder | 
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| General Description | Features | Datasheet | Package & Models | Samples & Pricing | Application Notes | 
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| Title | Size in Kbytes | Date |  View Online |  Download |  Receive via Email | 
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| 54AC273 Octal D Flip-Flop | 157 Kbytes | 2-Sep-98 | View Online | Download | Receive via Email | 
| 54AC273 Mil-Aero Datasheet MN54AC273-X | 108 Kbytes | View Online | Download | Receive via Email | 
| If you have trouble printing or viewing PDF file(s), see Printing Problems. | 
| Part Number | Package | Status | Models | Samples & Electronic Orders | Budgetary Pricing | Std Pack Size | Package Marking | |||||
| Type | Pins | MSL/Lead-Free Availability | Lead Time | Qty | SPICE | IBIS | Qty | $US each | ||||
| 5962-87756012A (54AC273LMQB) | LCC | 20 | Status | Full production | N/A | N/A |  | 50+ | $9.60 | rail of 50 | NSZSSXXYYA 54AC273 LMQB /QL> 5962- 87756012A | |
| 7-8 weeks | 500 | |||||||||||
| 5962-8775601RA (54AC273DMQB) | CERDIP | 20 | Status | Full production | N/A | N/A |  | 50+ | $6.40 | rail of 20 | NSZSSXXYYA> 54AC273DMQB /QL 5962-8775601RA | |
| 6-8 weeks | 500 | |||||||||||
| 5962-8775601SA (54AC273FMQB) | CERPACK | 20 | Status | Full production | N/A | N/A |  | 50+ | $9.60 | rail of 19 | NSZSSXXYYA> 54AC273FMQB QL 5962- 8775601SA | |
| 7-8 weeks | 500 | |||||||||||
| 54AC273WG-QML | CERPACK | 20 | Status | Full production | N/A | N/A | 50+ | $9.50 | tray of 30 | NSZSSXXYYA> 54AC273WG- QML 5962- 8775601ZA | ||
| 8-10 weeks | 500 | |||||||||||
| JM38510R75601BRA | CERDIP | 20 | Status | Full production | N/A | N/A | 50+ | $68.00 | rail of 20 | NSZSSXXYYA> JM38510R75601BRA 27014 | ||
| N/A | 0 | |||||||||||
| JM38510R75601BSA | CERPACK | 20 | Status | Full production | N/A | N/A | 50+ | $68.00 | rail of 19 | NSZSSXXYYA> 27014 JM38510 R75601BSA | ||
| N/A | 0 | |||||||||||
| JM38510/75601B2A | LCC | 20 | Status | Full production | N/A | N/A | 50+ | $13.60 | rail of 50 | NS JM38510 /75601B2A 27014 QS ZSSXXYYA> | ||
| 7-8 weeks | 500 | |||||||||||
| JM38510R75601B2A | LCC | 20 | Status | Full production | N/A | N/A | 50+ | $75.00 | rail of 50 | NS JM38510 R75601B2A 27014 QS ZSSXXYYA> | ||
| N/A | 0 | |||||||||||
| JM38510/75601BRA | CERDIP | 20 | Status | Full production | N/A | N/A |  | 50+ | $9.60 | rail of 20 | NS ZSSXXYYA> JM38510/75601BRA 27014 QS | |
| 6-8 weeks | 500 | |||||||||||
| JM38510/75601BSA | CERPACK | 20 | Status | Full production | N/A | N/A |  | 50+ | $12.30 | rail of 19 | NSZSSXXYYA> JM38510/ 75601BSA 27014 QS | |
| 7-8 weeks | 500 | |||||||||||
| JM54AC273BZA | CERPACK | 20 | Status | Full production | N/A | N/A | tray of N/A | NSZSSXXYYA> JM38510/ 75601BZA 27014 QS | ||||
| 9-11 weeks | 500 | |||||||||||
| JM38510R75601S2A | LCC | 20 | Status | Full production | N/A | N/A | 50+ | $138.00 | rail of 50 | NSZSSXXYYA 27014 Q > JM38510R 75601S2A | ||
| N/A | 0 | |||||||||||
| JM38510R75601SRA | CERDIP | 20 | Status | Full production | N/A | N/A | 50+ | $138.00 | rail of 20 | NS ZSSXXYYA> JM38510R75601SRA 27014 Q | ||
| N/A | 0 | |||||||||||
| JM54AC273SSA-FH | CERPACK | 20 | Status | Preliminary | N/A | N/A | rail of N/A | NSZSSXXYYA> 27014 Q JM38510F 75601SSA | ||||
| N/A | ||||||||||||
| JM38510R75601SSA | CERPACK | 20 | Status | Full production | N/A | N/A | 50+ | $138.00 | rail of 19 | NSZSSXXYYA> 27014 Q JM38510R 75601SSA | ||
| N/A | 0 | |||||||||||
| JM54AC273SZA-FH | CERPACK | 20 | Status | Preliminary | N/A | N/A | tray of N/A | NSZSSXXYYA 27014 Q> JM38510F 75601SZA | ||||
| N/A | ||||||||||||
| JM38510R75601SZA | CERPACK | 20 | Status | Full production | N/A | N/A | 50+ | $143.00 | tray of 30 | NSZSSXXYYA> 27014 Q JM38510R 75601SZA | ||
| N/A | 0 | |||||||||||
| The '273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR#) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR# input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. | 
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| Title | Size in Kbytes | Date |  View Online |  Download |  Receive via Email | 
|---|---|---|---|---|---|
| AN-925: Radiation Design Test Data for Advanced CMOS Product | 194 Kbytes | 5-Aug-95 | View Online | Download | Receive via Email | 
| If you have trouble printing or viewing PDF file(s), see Printing Problems. | 
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