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54ACT373
54ACT373 Product Folder |
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| General Description |
Features | Datasheet | Package & Models |
Samples & Pricing |
Application Notes |
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| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
|---|---|---|---|---|---|
| 54AC373 54ACT373 Octal Transparent Latch with TRI-STATE Outputs | 166 Kbytes | 14-Aug-98 | View Online | Download | Receive via Email |
| 54ACT373 Mil-Aero Datasheet MN54ACT373-X | 15 Kbytes | View Online | Download | Receive via Email |
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If you have trouble printing or viewing PDF file(s), see Printing Problems. |
| Part Number | Package | Status | Models | Samples & Electronic Orders | Budgetary Pricing | Std Pack Size | Package Marking | |||||
| Type | Pins | MSL/Lead-Free Availability | Lead Time | Qty | SPICE | IBIS | Qty | $US each | ||||
| 5962-87556012A (54ACT373LMQB) | LCC | 20 | Status | Full production | N/A | N/A |  | 50+ | $8.80 | rail of 50 | NSZSSXXYYA 54ACT373 LMQB /QL> 5962- 87556012A | |
| 8-10 weeks | 500 | |||||||||||
| 5962-8755601RA (54ACT373DMQB) | CERDIP | 20 | Status | Full production | N/A | N/A | | 50+ | $6.40 | rail of 20 | NSZSSXXYYA> 54ACT373DMQB /QL 5962-8755601RA | |
| 8-10 weeks | 500 | |||||||||||
| 5962-8755601SA (54ACT373FMQB) | CERPACK | 20 | Status | Full production | N/A | N/A | | 50+ | $8.80 | rail of 19 | NSZSSXXYYA> 54ACT373FMQB QL 5962- 8755601SA | |
| 8-10 weeks | 500 | |||||||||||
| 54ACT373DM-MLS | CERDIP | 20 | Status | Full production | N/A | N/A | 50+ | $152.00 | rail of 20 | NSZSSXXYYA> 54ACT373DM-MLS | ||
| N/A | 0 | |||||||||||
| 54ACT373FM-MLS | CERPACK | 20 | Status | Full production | N/A | N/A | 50+ | $152.00 | rail of 19 | NSZSSXXYYA> 54ACT373FM-MLS | ||
| N/A | 0 | |||||||||||
| Obsolete Part | Alternate Part or Supplier | Source | Last Time Buy Date |
|---|---|---|---|
| 54ACT373DM. | 54ACT373DMQB | NATIONAL SEMICONDUCTOR | 12/04/2001 |
The 'AC/'ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE#) is LOW. When OE# is HIGH, the bus output is in the high impedance state. |
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| Title | Size in Kbytes | Date | View Online |
Download |
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|---|---|---|---|---|---|
| AN-932: SEU and Latch Up Tolerant Advanced CMOS Technology | 186 Kbytes | 5-Jan-96 | View Online | Download | Receive via Email |
| AN-989: AN-989 Single Event Upset and Latchup Considerations for CMOS Devices Operated at 3.3 V | 91 Kbytes | 6-Oct-99 | View Online | Download | Receive via Email |
| AN-925: Radiation Design Test Data for Advanced CMOS Product | 194 Kbytes | 5-Aug-95 | View Online | Download | Receive via Email |
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If you have trouble printing or viewing PDF file(s), see Printing Problems. |
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