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54ACT377  Product Folder

Octal D Flip-Flop with Clock Enable
General
Description		 Features Datasheet Package
& Models		 Samples
& Pricing

Parametric Table Parametric Table
Temperature Min (deg C) -55 
Temperature Max (deg C) 125 

Datasheet

TitleSize in KbytesDate
View Online
Download
Receive via Email
54AC377 54ACT377 Octal D Flip-Flop with Clock Enable 177 Kbytes 2-Feb-99 View Online Download Receive via Email
54ACT377 Mil-Aero Datasheet MN54ACT377-X 13 Kbytes   View Online Download Receive via Email

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Package Availability, Models, Samples & Pricing

Part NumberPackageStatusModelsSamples &
Electronic
Orders		Budgetary PricingStd
Pack
Size		Package
Marking
TypePinsMSL/Lead-Free AvailabilityLead
Time		QtySPICEIBISQty$US each
5962-8769701M2A
(54ACT377LMQB)		LCC20StatusLifetime buyN/AN/A 50+$10.20rail
of
50		NSZSSXXYYA
54ACT377
LMQB /QL>
5962-
8769701M2A
8 weeks500
5962-8769701MRA
(54ACT377DMQB)		CERDIP20StatusFull productionN/AN/A 
Buy Now		50+$8.60rail
of
20		NSZSSXXYYA>
54ACT377DMQB /QL
5962-8769701MRA
6-8 weeks500
5962-8769701MSA
(54ACT377FMQB)		CERPACK20StatusFull productionN/AN/A 50+$10.20rail
of
19		NSZSSXXYYA>
54ACT377FMQB
QL 5962-
8769701MSA
8-9 weeks500
5962-8769701B2ALCC20StatusFull productionN/AN/A 50+$13.60rail
of
50		NSZSSXXYYA
QS >
5962-
8769701B2A
8 weeks500
5962-8769701BRACERDIP20StatusFull productionN/AN/A 50+$9.60rail
of
20		NS ZSSXXYYA>
5962-8769701BRA
27014 QS
10-12 weeks500
5962-8769701BSACERPACK20StatusFull productionN/AN/A 50+$13.60rail
of
19		NSZSSXXYYA>
5962-
8769701BSA
27014 QS
8-10 weeks500
5962-8769701SRACERDIP20StatusFull productionN/AN/A 50+$138.00rail
of
20		NS ZSSXXYYA>
5962-8769701SRA
27014 Q
N/A0
5962-8769701SSACERPACK20StatusFull productionN/AN/A 50+$138.00rail
of
19		NSZSSXXYYA>
5962-
8769701SSA
27014 Q
N/A0

Obsolete Parts

Obsolete PartAlternate Part or SupplierSourceLast Time Buy Date
54ACT377DM
54ACT377DMQB
NATIONAL SEMICONDUCTOR
03/09/99
54ACT377LMQB.
NATIONAL
5962-8769701M2A
09/01/2004

General Description

The 'AC/'ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE#) is LOW.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE# input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

Features

  • ICC reduced by 50%
  • Ideal for addressable register applications
  • Clock enable for address and data synchronization applications
  • Eight edge-triggered D flip-flops
  • Buffered common clock
  • Outputs source/sink 24 mA
  • See '273 for master reset version
  • See '373 for transparent latch version
  • See '374 for TRI-STATE version
  • 'ACT377 has TTL-compatible inputs
  • Standard Microcircuit Drawing (SMD) -'AC377: 5962-88702 -'ACT377: 5962-87697
[Information as of 15-Jan-2004]

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