54ACTQ273  Product Folder

The ACTQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR#) input load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.

All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR# input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.

The ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.

• I_CC reduced by 50%
• Guaranteed simultaneous switching noise level and dynamic threshold performance
• Improved latch-up immunity
• Buffered common clock and asynchronous master reset
• Outputs source/sink 24 mA
• Faster prop delays than the standard 'AC/'ACT273
• 4 kV minimum ESD immunity
• Standard Microcircuit Drawing (SMD) 5962-89735