54ACTQ377  Product Folder

The ACTQ377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE#) is LOW.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE# input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

The ACTQ377 utilizes FACT Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.

• Ideal for addressable register applications
• Clock enable for address and data synchronization applications
• Eight edge-triggered D flip-flops
• Buffered common clock
• Outputs source/sink 24 mA
• See '273 for master reset version
• See '373 for transparent latch version
• See '374 for TRI-STATE version
• Guaranteed simultaneous switching noise level and dynamic threshold performance
• TTL-compatible inputs and outputs
• Standard Microcircuit Drawing (SMD) 5962-9219001