HOME HOME SELECT DESIGN BUY EXPLORE About Us Support My Profile Search

 Products > Military/Aerospace > Logic > FAST > 54F74

54F74  Product Folder

Dual D-Type Positive Edge-Triggered Flip-Flop
General
Description		 Features Datasheet Package
& Models		 Samples
& Pricing

Parametric Table Parametric Table
Temperature Min (deg C) -55 
Temperature Max (deg C) 125 

Datasheet

TitleSize in KbytesDate
View Online
Download
Receive via Email
54F74 Dual D-Type Positive Edge-Triggered Flip-Flop 159 Kbytes 9-Dec-97 View Online Download Receive via Email
54F74 Mil-Aero Datasheet MN54F74-X 23 Kbytes   View Online Download Receive via Email

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Package Availability, Models, Samples & Pricing

Part NumberPackageStatusModelsSamples &
Electronic
Orders		Budgetary PricingStd
Pack
Size		Package
Marking
TypePinsMSL/Lead-Free AvailabilityLead
Time		QtySPICEIBISQty$US each
54F74LMQBLCC20StatusFull productionN/AN/A 
Buy Now		50+$4.89rail
of
50		NSZSSXXYYA
54F74
LMQB /QL
>
6-8 weeks500
54F74DMQBCERDIP14StatusFull productionN/AN/A 
Buy Now		50+$1.63rail
of
25		NSZSSXXYYA>
54F74DMQB
QL
6-8 weeks500
54F74FMQBCERPACK14StatusFull productionN/AN/A 50+$4.00rail
of
19		NSZSSXXYYA>
54F74FMQB
QL
7-8 weeks500
JM38510/34101B2ALCC20StatusFull productionN/AN/A 50+$4.50rail
of
50		NS JM38510
/34101B2A
27014 QS
ZSSXXYYA>
7-8 weeks500
JM38510/34101BCACERDIP14StatusFull productionN/AN/A 
Buy Now		50+$2.00rail
of
25		NS ZSSXXYYA>
JM38510/34101BCA
27014 QS
6-8 weeks500
JM38510/34101BDACERPACK14StatusFull productionN/AN/A 
Buy Now		50+$4.08rail
of
19		NSZSSXXYYA>
JM38510/
34101BDA
27014 QS
7-8 weeks500
JM38510/34101SCACERDIP14StatusFull productionN/AN/A 50+$145.00rail
of
25		NS ZSSXXYYA>
JM38510/34101SCA
27014
N/A0
JM38510/34101SDACERPACK14StatusFull productionN/AN/A 50+$145.00rail
of
19		NSZSSXXYYA
27014 Q>
JM38510/
34101SDA
N/A0

Obsolete Parts

Obsolete PartAlternate Part or SupplierSourceLast Time Buy Date
54F74DM.
54F74DMQB
NATIONAL SEMICONDUCTOR
09/04/2001

General Description

The 'F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q#) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.

Asynchronous Inputs:

LOW input to S#D sets Q to HIGH level

LOW input to C#D sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on C#D and S#D

makes both Q and Q# HIGH

Features

  • Guaranteed 4000V minimum ESD protection
[Information as of 15-Jan-2004]

Website Guide • About "Cookies" • National is QS 9000 Certified • Privacy/Security Statement • Contact Us/Feedback
Site Terms & Conditions of Use • Copyright 2003© National Semiconductor Corporation