54FCT377  Product Folder

The 'FCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE#) is LOW.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE# input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

• Clock enable for address and data synchronization applications
• Eight edge-triggered D flip-flops
• Buffered common clock
• See 'FCT273 for master reset version
• See 'FCT373 for transparent latch version
• See 'FCT374 for TRI-STATE® version
• TTL input and output level compatible
• CMOS power consumption
• Output sink capability of 32 mA, source capability of 12 mA
• Standard Microcircuit Drawing (SMD) 5962-8762701