54LS365 Product Folder |
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| General Description |
Features | Datasheet | Package & Models |
Samples & Pricing |
| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| 54LS365A DM54LS365A Hex TRI-STATE(RM) Buffers | 131 Kbytes | 7-Jan-98 | View Online | Download | Receive via Email |
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| Part Number | Package | Status | Models | Samples & Electronic Orders | Budgetary Pricing | Std Pack Size | Package Marking | |||||
| Type | Pins | MSL/Lead-Free Availability | Lead Time | Qty | SPICE | IBIS | Qty | $US each | ||||
| JD54LS365B2A | LCC | 20 | Status | Full production | N/A | N/A | rail of N/A | NS JM38510 /32201B2A 27014 QS ZSSXXYYA> | ||||
| 7-9 weeks | 500 | |||||||||||
| JM38510/32201BEA | CERDIP | 16 | Status | Full production | N/A | N/A | | 50+ | $2.75 | rail of 25 | NS ZSSXXYYA> JM38510/32201BEA 27014 QS | |
| 6-8 weeks | 500 | |||||||||||
This device contains six independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs. |
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