DS34LV86T Product Folder |
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| General Description |
Features | Datasheet | Package & Models |
Samples & Pricing |
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| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| DS34LV86T 3V Enhanced CMOS Quad Differential Line Receiver | 154 Kbytes | 11-Mar-02 | View Online | Download | Receive via Email |
| DS34LV86T 3V Enhanced CMOS Quad Differential Line Receiver (JAPANESE) |
108 Kbytes |
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If you have trouble printing or viewing PDF file(s), see Printing Problems. |
| Part Number | Package | Status | Models | Samples & Electronic Orders | Budgetary Pricing | Std Pack Size | Package Marking | |||||
| Type | Pins | MSL/Lead-Free Availability | Lead Time | Qty | SPICE | IBIS | Qty | $US each | ||||
| DS34LV86TM | SOIC NARROW | 16 | Status | Full production | N/A | N/A | 1K+ | $1.18 | rail of 48 | NSUZXYTT DS34LV86 TM | ||
| 8-10 weeks | 10000 | |||||||||||
| DS34LV86TMX | SOIC NARROW | 16 | Status | Full production | N/A | N/A | 1K+ | $1.18 | reel of 2500 | NSUZXYTT DS34LV86 TM | ||
| 8-10 weeks | 10000 | |||||||||||
| DS34LV86 MDC | Unpackaged Die | Full production | N/A | N/A | tray of N/A | - | ||||||
| N/A | 0 | |||||||||||
| DS34LV86 MWC | Wafer | Full production | N/A | N/A | wafer jar of N/A | - | ||||||
| N/A | 0 | |||||||||||
| Obsolete Part | Alternate Part or Supplier | Source | Last Time Buy Date |
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| DS34LV86TN | NONE | NONE | 03/08/2000 |
The DS34LV86T is a high speed quad differential CMOS receiver that meets the requirements of both TIA/EIA-422-B and ITU-T V.11. The CMOS DS34LV86T features typical low static ICC of 9 mA which makes it ideal for battery powered and power conscious applications. The TRI-STATE® enables, EN, allow the device to be disabled when not in use to minimize power consumption. The dual enable scheme allows for flexibility in turning receivers on and off. The receiver output (RO) is guaranteed to be High when the inputs are left open. The receiver can detect signals as low as ±200 mV over the common mode range of ±10V. The receiver outputs (RO) are compatible with TTL and LVCMOS levels. |
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