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PC87383  Product Folder

Legacy-Reduced SuperI/O with Fast Infrared Port, Serial Port Parallel Port and GPIOs for Portable Applications
Generic P/N 87383
General
Description
Features Datasheet Package
& Models
Samples
& Pricing

Datasheet

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PC87383 Legacy-Reduced SuperI O with Fast Infrared Port, Serial Port Parallel Port and GPIOs for Portable Applications 894 Kbytes 13-Jan-04 View Online Download Receive via Email

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Package Availability, Models, Samples & Pricing

Part NumberPackageStatusModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
TypePinsMSL/Lead-Free AvailabilityLead
Time
QtySPICEIBISQty$US each
PC87383-VSTQFP64StatusPreliminaryN/AN/A   tray
of
N/A
-
12 weeks0

General Description

The PC87383, a member of the National Semiconductor LPC SuperI/O family, is targeted for a wide range of portable applications. The PC87383 is PC2001 and ACPI compliant, and features Fast Infrared port (FIR, IrDA 1.1 compliant), Serial Port, Parallel Port and General-Purpose Input/Output (GPIO) support for a total of 21 ports.


Outstanding Features

  • LPC bus interface, based on IntelÆs LPC Interface Specification Revision 1.1, August 2002 (supports CLKRUN and LPCPD signals)
  • Fast Infrared port
  • PC2001 and ACPI Revision 2.0 compliant
  • Serial IRQ support (15 options)
  • Protection features, including GPIO lock and pin configuration lock
  • 21 GPIO ports, including 14 with ôassert IRQö capability
  • XOR Tree and TRI-STATE™ device pins (or ICT) testability modes.
  • 5V tolerant and back-drive protected pins (except LPC bus pins)
  • 64-pin TQFP package

Features

  • LPC System Interface
    • Synchronous cycles, up to 33 MHz bus clock
    • 8-bit I/O cycles
    • Up to four 8-bit DMA channels
    • LPCPD and CLKRUN support
    • Implements PCI mobile design guide recommendation (PCI Mobile Design Guide 1.1, Dec. 18, 1998)
  • PC2001 and ACPI Compliant
    • PnP Configuration Register structure
    • Flexible resource allocation for all logical devices
      • Relocatable base address
      • ❏ 15 IRQ routing options
      • Three optional 8-bit DMA channels (where applicable) selected from four possible DMA channels
  • Clock Sources
    • 14.318 MHz or 48 MHz clock input
    • LPC clock, up to 33 MHz
  • Power Supply
    • 3.3V supply operation
    • All pins are 5V tolerant, except LPC bus pins
    • All pins are back-drive protected, except LPC bus pins
  • 21 General-Purpose I/O (GPIO) Ports
    • 14 support assert IRQ
    • Programmable drive type for each output pin (opendrain, push-pull or output disable)
    • Programmable option for internal pull-up resistor on each input pin
    • Output lock option
    • Programmable option for input debounce mechanism
  • Serial Port (SP1)
    • Software compatible with the 16550A and the 16450
    • Shadow register support for write-only bit monitoring
    • UART data rates up to 1.5 Mbaud
  • IEEE 1284-compliant Parallel Port
    • ECP, with Level 2 (14 mA sink and source output buffers)
    • Software or hardware control
    • Enhanced Parallel Port (EPP) compatible with EPP 1.7 and EPP 1.9
    • Supports EPP as mode 4 of the Extended Control Register (ECR)
    • Selection of internal pull-up or pull-down resistor for Paper End (PE) pin
    • Supports a demand DMA mode mechanism and a DMA fairness mechanism for improved bus utilization
    • Protection circuit that prevents damage to the parallel port when a printer connected to it is powered up or is operated at high voltages (in both cases, even if the PC87383 is in power-down state)
  • Fast Infrared Port (FIR)
    • Software compatible with the 16550A and the 16450
    • Shadow register support for write-only bit monitoring
    • FIR IrDA 1.1 compliant
    • HP-SIR
    • ASK-IR option of SHARP-IR
    • DASK-IR option of SHARP-IR
    • Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS 80
    • DMA support: 1 or 2 channels
  • Strap Configuration
    • Base Address (BADDR) strap to determine the base address of the Index-Data register pair
    • Strap Inputs to select testability mode
  • Testability
    • XOR Tree
    • TRI-STATE device pins
[Information as of 15-Jan-2004]