HOME HOME SELECT DESIGN BUY EXPLORE About Us Support My Profile Search

 Products > Analog - Interface > LVDS Circuits > SCAN LVDS Circuits > SCAN921260

SCAN921260  Product Folder

six 1 to 10 deserializers with IEEE 1149.1 and at-speed BIST
Generic P/N 921260
General
Description
Features Datasheet Package
& Models
Samples
& Pricing
Application
Notes

Parametric Table Parametric Table
Temperature Min (deg C) -40 
Temperature Max (deg C) 85 
Supply Voltage (Volt) 3.30 
OtherSupply Voltage Undefined 
Function Deserializer 
Channels (Channels) 6 
Data Rate (Mbps) 660 
Total Throughput (Mbps) 3960 
JTAG (IEEE1149.1) or BIST Yes 

Datasheet

TitleSize in KbytesDate
View Online

Download

Receive via Email
SCAN921260 X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST 379 Kbytes 22-Sep-03 View Online Download Receive via Email

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Package Availability, Models, Samples & Pricing

Part NumberPackageStatusModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
TypePinsMSL/Lead-Free AvailabilityLead
Time
QtySPICEIBISQty$US each
SCAN921260UJBXLBGA196StatusPreliminaryN/Ascan921260ujb.ibs   reel
of
N/A
NSUZXYYTT
SCAN921260
UJB
N/A0
SCAN921260UJBLBGA196StatusFull productionN/Ascan921260ujb.ibs 
Buy Now
1K+$24.00tray
of
119
NSUZXYYTT
SCAN921260
UJB
6 weeks0

General Description

The SCAN921260 integrates six deserializer devices into a single chip. The SCAN921260 can simultaneously deserialize up to six data streams that have been serialized by the National Semiconductor SCAN921023 Bus LVDS serializer. The device also includes a seventh serial input channel that serves as a redundant input.

Each deserializer block in the SCAN921260 operates independently with its own clock recovery circuitry and lock-detect signaling.

The SCAN921260 uses a single +3.3V power supply with an estimated power dissipation of 1.2W at 3.3V with a PRBS-15 pattern. Refer to the Connection Diagrams for packaging information.

Features

  • IEEE 1149.1 (JTAG) Compliant and at-speed BIST test modes
  • Deserializes one to six BusLVDS input serial data streams with embedded clocks
  • Seven selectable serial inputs to support n+1 redundancy of deserialized streams
  • Seventh channel has single pin monitor output that reflects input from seventh channel input
  • Parallel clock rate up to 66MHz
  • On chip filtering for PLL
  • High impedance inputs upon power off (Vcc = 0V)
  • Single power supply at +3.3V
  • 196-pin LBGA package (Low-profile Ball Grid Array) package
  • Industrial temperature range operation: -40 to +85

Application Notes

TitleSize in KbytesDate
View Online

Download

Receive via Email
AN-1217: Application Note 1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask 339 Kbytes 30-May-02 View Online Download Receive via Email

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 15-Jan-2004]