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SCAN926260  Product Folder

Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST
Generic P/N 926260
General
Description
Features Datasheet Package
& Models
Samples
& Pricing

Parametric Table Parametric Table
Temperature Min (deg C) -40 
Temperature Max (deg C) 85 
Supply Voltage (Volt) 3.30 
OtherSupply Voltage Undefined 
Function Deserializer 
Channels (Channels)
Data Rate (Mbps) 660 
Total Throughput (Mbps) 3960 
JTAG (IEEE1149.1) or BIST Yes 

Datasheet

TitleSize in KbytesDate
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SCAN926260 Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST 369 Kbytes 8-Dec-03 View Online Download Receive via Email

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Package Availability, Models, Samples & Pricing

Part NumberPackageStatusModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
TypePinsMSL/Lead-Free AvailabilityLead
Time
QtySPICEIBISQty$US each
SCAN926260TUFLBGA196StatusFull productionN/Ascan926260tuf.ibs 
Buy Now
1K+$24.00tray
of
119
NSUZXYYTT
SCAN926260T
UF
BBBBB
2-6 weeks3000

General Description

The SCAN926260 integrates six 10-bit deserializer devices into a single chip. The SCAN926260 can simultaneously deserialize up to six data streams that have been serialized by National Semiconductor's 10-bit Bus LVDS serializers. In addition, the SCAN926260 is compliant with IEEE standard 1149.1 and also features an At-Speed Built-In Self Test (BIST). For more details, please see the sections titled "IEEE 1149.1 Test Modes" and "BIST Alone Test Modes."

Each deserializer block in the SCAN926260 has it's own powerdown pin (PWRDWN[n]#)and operates independently with its own clock recovery circuitry and lock-detect signaling. In addition, a master powerdown pin (MS_PWRDWN#) which puts all the entire device into sleep mode is provided.

The SCAN926260 uses a single +3.3V power supply and consumes 1.2W at 3.3V with a PRBS-15 pattern on all channels at 660Mbps.

Features

  • Deserializes one to six Bus LVDS input serial data streams with embedded clocks
  • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test modes
  • Parallel clock rate 16-66MHz
  • On chip filtering for PLL
  • High impedance inputs upon power off (Vcc = 0V)
  • Single power supply at +3.3V
  • 196-pin LBGA package (Low-profile Ball Grid Array) package
  • Industrial temperature range operation: -40°C to +85°C
  • ROUTn[0:9] and RCLKn default high when channel is not locked
  • Powerdown per channel to conserve power on unused channels
[Information as of 15-Jan-2004]