SCAN921224  Product Folder

The SCAN921023 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The SCAN921224 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock. Both devices are compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST#). IEEE 1149.1 features provide the designer or test engineer access to the backplane or cable interconnects and the ability to verify differential signal integrity to enhance their system test strategy. The pair of devices also features an at-speed BIST mode which allows the interconnects between the Serializer and Deserializer to be verified at-speed.

The SCAN921023 transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock guarantees a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the SCAN921023 output pins into TRI-STATE to achieve a high impedance state. The PLL can lock to frequencies between 20 MHz and 66 MHz.

• IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test mode.
• Clock recovery from PLL lock to random data patterns.
• Guaranteed transition every data transfer cycle
• Chipset (Tx + Rx) power consumption < 500 mW (typ) @ 66 MHz
• Single differential pair eliminates multi-channel skew
• Flow-through pinout for easy PCB layout
• 660 Mbps serial Bus LVDS data rate (at 66 MHz clock)
• 10-bit parallel interface for 1 byte data plus 2 control bits
• Synchronization mode and LOCK indicator
• Programmable edge trigger on clock
• High impedance on receiver inputs when power is off
• Bus LVDS serial output rated for 27 load
• Small 49-lead BGA package