SCANSTA111 Product Folder |
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| General Description |
Features | Datasheet | Package & Models |
Samples & Pricing |
Reliability Metrics |
Application Notes |
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| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
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| SCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port | 520 Kbytes | 3-Jul-03 | View Online | Download | Receive via Email |
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| Part Number | Package | Status | Models | Samples & Electronic Orders | Budgetary Pricing | Std Pack Size | Package Marking | |||||
| Type | Pins | MSL/Lead-Free Availability | Lead Time | Qty | SPICE | IBIS | Qty | $US each | ||||
| SCANSTA111MTX | TSSOP | 48 | Status | Full production | N/A | N/A | reel of N/A | NSUZXYTT SCANSTA111MT | ||||
| N/A | 0 | |||||||||||
| SCANSTA111MT | TSSOP | 48 | Status | Full production | N/A | N/A | | 1K+ | $5.75 | rail of 38 | NSUZXYTT SCANSTA111MT | |
| 2-4 weeks | 3000 | |||||||||||
| SCANSTA111SM | FBGA | 49 | Status | Full production | N/A | sta111sm.ibs | | 1K+ | $5.75 | tray of 416 | NSUZXYTT SCANSTA111 SM | |
| 2-6 weeks | 1000 | |||||||||||
| SCANSTA111SMX | FBGA | 49 | Status | Full production | N/A | sta111sm.ibs | 1K+ | $5.75 | reel of 2000 | NSUZXYTT SCANSTA111 SM | ||
| 6 weeks | 0 | |||||||||||
| SCANSTAEVK | evaluation board | Preliminary | N/A | N/A | | 1+ | $1500.00 | 1 | - | |||
| N/A | 0 | |||||||||||
| SCANSTA111 MDC | Unpackaged Die | Full production | N/A | N/A | tray of N/A | - | ||||||
| N/A | 0 | |||||||||||
| SCANSTA111 MWC | Wafer | Full production | N/A | N/A | wafer jar of N/A | - | ||||||
| N/A | 0 | |||||||||||
The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA111 supports up to 3 local IEEE1149.1 scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested. |
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| Part Number | Process | Early Failure Rate - Rejects | Sample Size (EFR) | PPM * | Rel. Rejects | Device Hours | Long Term Failure Rates (FITS) | MTTF |
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| SCANSTA111 MDC | CMOS7 | 2 | 14200 | 141 | 0 | 800000 | 5 | 226190940 |
| SCANSTA111 MWC | CMOS7 | 2 | 14200 | 141 | 0 | 800000 | 5 | 226190940 |
| SCANSTA111MT | CMOS7 | 2 | 14200 | 141 | 0 | 800000 | 5 | 226190940 |
| SCANSTA111MTX | CMOS7 | 2 | 14200 | 141 | 0 | 800000 | 5 | 226190940 |
| SCANSTA111SM | CMOS7 | 2 | 14200 | 141 | 0 | 800000 | 5 | 226190940 |
| SCANSTA111SMX | CMOS7 | 2 | 14200 | 141 | 0 | 800000 | 5 | 226190940 |
| Title | Size in Kbytes | Date | View Online |
Download |
Receive via Email |
|---|---|---|---|---|---|
| AN-1259: Application Note 1259 SCANSTA112 Designers Reference | 353 Kbytes | 17-Apr-03 | View Online | Download | Receive via Email |
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If you have trouble printing or viewing PDF file(s), see Printing Problems. |
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