Objective:

To review and test the advanced concepts of PLL circuit design, using reference material from Wireless Lessons 1 through 5.

Online Seminars:

Advantages and Pitfalls of Using Fractional N PLLs (online seminar notes),
February 27, 2003, by Dean Banerjee
The rise of Fractional N PLLs, and especially Sigma Delta Fractional N PLLs brings the opportunity for significant performance enhancements in some applications, but other applications favor the use of Integer N PLLs. This presentation concentrates on performance criteria of lock time, phase noise and spur levels. 

Loop Filter Optimization,
April 19, 2001, by Dean Banerjee, Deborah Brown, and Khang Nguyen
This seminar discusses various issues related to passive loop filter designs and presents new techniques using EasyPLL for optimizing passive loop filters for better performance.

Reading Assignment:

1. Non-PLL Radio Frequency presentation and slide notes
   
   
2. PLL Building Blocks presentation and slide notes
   
   
3. PLL Performance presentation and slide notes
   
   
4. Fractional N PLLs presentation and slide notes
   
   
5. Loop Filter Optimization presentation (and notes) from online seminar
   
   
6. WEBENCH™ EasyPLL Online Simulation Tools help
   
   
7. WIRELESS.NATIONAL.COM presentation and slide notes

Additional Resources:

• PLL Performance, Simulation and Design, by Dean Banerjee
  
  
• Single Integer PLL Parametric Selection Guide: Wireless.national.com

Research Assignment:

1. What are the three different types of fractional compensation methods? Briefly define them. check answer
   
   
2. What performance parameters does the loop filter affect? check answer
   
   
3. If I keep the same comparison frequency, but double the N counter value, what is the impact on phase noise inside the loop bandwidth? check answer
   
   
4. If a 1 GHz signal and a 900 MHz signal are input to a mixer:
   What are the frequencies of the two intermodulation products? check answer
   
   
5. If I have a comparison frequency of 200 KHz, approximately what is the minimum loop bandwidth I can have to change from 889 - 915 MHz to a 1 KHz tolerance in less than 500 uS? check answer
   

Program Coordinator/Professor

Dean Banerjee

Dean Banerjee is a Senior Wireless Applications Engineer with National Semiconductor's Wireless Products division and is the author of "PLL Performance, Simulation, and Design". During this time, he has assisted in the development and support of various PLL synthesizer chips.

Quiz:

Take the Advanced Quizzes in the following topics:

1. Non-PLL Radio Frequency (RF) Basics
   
   
2. PLL Building Blocks
   
   
3. PLL Performance
   
   
4. Fractional PLLs
   
   
5. National's PLL tools

Answer all questions correctly to receive advanced certificates from Dean Bob Pease.